The present invention relates to a semiconductor device including a bipolar transistor, and particularly to a structure of a semiconductor device including a multi-emitter bipolar transistor of a self-align type.
Along with remarkable development of mobile communication equipment such as a mobile telephone or a PHS (Personal Handy-phone System) or computer networks, high-performance and inexpensive bipolar transistors are earnestly pursued for realizing high-speed and low-cost communication circuits.
An promising approach is application of a self-align type bipolar transistor having emitter and base leading electrodes formed of poly-Si (poly-crystalline silicon) such as described in "Optimization of shallow and deep trench isolation structures for ultra-high-speed bipolar LSIs" by Itoh et al., pp. 104-107, proceedings IEEE 1992 Bipolar Circuits and Technology Meeting.
FIG. 11A illustrates a plan layout of a conventional example (here-after called the first conventional example) of a bipolar transistor of this type, whereof a sectional view cut along a line F-F' of FIG. 11A is illustrated in FIG. 11B.
In the first conventional example of FIGS. 11A and 11B, an n.sup.+ -type buried layer 202 is selectively formed on a p-type Si substrate 201 and an n-type epitaxial layer 203 is formed thereon, to configure a bipolar transistor in a region surrounded by a first element-isolation film 204.
An extrinsic base region 213, an intrinsic base region 214, and a collector leading region 206 for leading out the n.sup.+ -type buried layer 202 are formed in a region surrounded by a second element-isolation film 205. The extrinsic base region 213 is led out by a base leading electrode 209 made of poly-Si, and an emitter region 215 is led out by an emitter leading electrode 212 also made of poly-Si. The base leading electrode 209 and the emitter leading electrode 212 are isolated from each other by a first and a second insulation film 210 and 211. The collector leading region 206, the emitter leading electrode 212 and the base leading electrode 209 are connected to a collector wiring 219a, an emitter wiring 219b and a base wiring 219c, respectively, through respective one of contact plugs 218a, 218b and 218c which are formed penetrating through an inter-layer insulation film 217.
In FIG. 11B, the base diffusion width a, the collector-base isolation length b and the separation length c between two wirings are designed to be respective minimum values which process factors allow.
The above structure of the self-align type bipolar transistor is determined in consideration of following factors.
1) It is generally effective for performance improvement of a bipolar transistor to minimize an area size of its emitter/base formation region. For this purpose, the base diffusion width a of FIG. 11B should be made as narrow as possible for minimizing the size of the emitter/base formation region 208.
2) The collector-base isolation length b of FIG. 11B should be as small as possible for reducing parasitic capacitance of the bipolar transistor, provided that it is longer than an isolation length determined from the collector-base breakdown voltage, and usually designed to be a minimum value allowed by the process factors.
3) The wiring width of the emitter and the collector electrode should be as wide as possible, for improving wiring reliability of the self-align type bipolar transistor wherein on-current of several mA to several 10 mA flows.
It is from these reasons that the contact plug 218c of the base wiring 219c cannot be formed directly upon the extrinsic base region 213, when the separation between the emitter wiring 219b and the base wiring 219c is set to have the minimum length c, and should be positioned on the second element-isolation film 205 to be connected indirectly to the extrinsic base region 213 by way of the base leading electrode 209 formed along the surface of the second-element isolation film 205.
For improving high-frequency performance of the self-align type bipolar transistor, the maximum oscillation frequency fmax should be made high and the maximum oscillation frequency fmax is in inverse proportion to the base resistance. Therefore, a structure having two base electrodes at both sides of the emitter electrode is often applied for reducing the base resistance, instead of the basic structure having one electrode for each of the emitter, the collector and the base as illustrated in FIGS. 11A and 11B. Furthermore, a multi-emitter structure having more than one emitter/base formation regions is sometimes applied for increasing current capacity of the self-align type bipolar transistor.
As a second conventional example, a self-align type bipolar transistor having a multi-emitter structure provided with base electrodes ranged at both sides of each emitter is briefly described referring to FIGS. 12A and 12B. FIG. 12A illustrates a plan layout of the multi-emitter bipolar transistor of the second conventional example, whereof a sectional view cut along a line G-G' is illustrated in FIG. 12B.
As shown in FIG. 12A, the contact holes for emitter, collector and base electrodes are arranged in an order of collector-base-emitter-base-collector-base-emitter-base-collector form left to right of the line G-G', and the contact plugs 218a, 218b and 218c of the respective electrodes are aligned straight.
Each element of the second conventional example of FIG. 12B is formed in a similar way with the corresponding element of the first conventional example of FIGS. 11A and 11B. However, the collector-base isolation length d of the second element-isolation film 205 is forced to be wider in FIG. 12B than the collector-base isolation length b of FIG. 11B, because of base wirings 219c each provided between a collector wiring 219a and an emitter wiring 219b provided upon the second element-isolation film 205 for reducing the base resistance, which were not provided there in the first conventional example of FIG. 11B.
Now, another example of the multi-emitter bipolar transistor is briefly described as a third conventional example referring to FIGS. 13A and 13B. FIG. 13A illustrates a plan layout of the multi-emitter bipolar transistor according to the third conventional example, and FIG. 13B is a sectional view cut along a line H-H' of FIG. 13A.
The structure of the third conventional example of FIGS. 13A and 13B, wherein the central collector wiring and corresponding elements of the second conventional example of FIGS. 12A and 12B are omitted, is to be applied in a circuit where the collector resistance is not required to be so low, and a collector, a base, an emitter, a base, an emitter and a collector are arranged in this order from left to right of FIG. 13A.
Here also, the contact plugs 218a, 218b and 218c of the respective electrodes are aligned straight.
As the number of collector electrodes is reduced from three to two, the whole size of the multi-emitter bipolar transistor can be made smaller according to the third conventional example than the second conventional example. However, when each individual element has the same size, the collector-base isolation length d of FIG. 13B is the same to the collector-base isolation length d of FIG. 12B, remaining wider than the collector-base isolation length b of FIG. 11B.
As heretofore described, the multi-emitter structure is applied for improving transistor characteristics of the self-align type bipolar transistor. However, the multi-emitter structure of the self-align type bipolar transistor is conventionally accompanied with a problem that the collector-base isolation length d is forced to be wider as illustrated in FIGS. 12A and 12B or in FIGS. 13A and 13B than the minimum value b of the collector-base isolation length which can be achieved in the basic structure as illustrated in FIGS. 11A and 11B wherein only one electrode is provided for each of the emitter, the collector and the base.
This problem results in not only obstruction of high-integration and miniaturization of semiconductor integrated circuits but also degradation of high-frequency performance of the bipolar transistor, due to increase of collector resistance, collector-base capacitance and collector-substrate capacitance of the bipolar transistor.